We offer for foundries and design houses a new RC substrate tool, fully compliant with circuit simulators, to detect post-layout noise degradation in mixed-signal and RF circuits.
PN Aware RC is intended for simulation of CMOS circuits where high-frequency switching circuits are present. It allows to detect substrate noise coupling paths and to find the proper shielding strategies to meet your specifications.
PN Solutions developed custom models for substrate extraction on advanced technology nodes which do not need substrate profiling information. SOI and BCD processes are supported and the model cards includes non-linear capacitive elements.
With a proprietary extraction algorithm all kind of shapes can be analysed from a LVS clean layout. In few seconds your post-layout netlist will include not only the RC parasitic elements of the metal routings but also of the substrate.
PN Aware RC is fully embedded in Cadence environment. From the layout extraction, you can simulate your original schematic with the extracted substrate RC network. By using the original testbench, there is no need of defining additional substrate ports.