PN Aware

We offer for foundries and design houses an innovative Substrate tool, fully compliant with circuit simulators, to detect post-layout latch-up risks.

PN Aware is intended for simulation in high-voltage CMOS circuits where power stage induced substrate noise is present. It allows to detect possible failures and to optimize the layout floorplan for complex mixed-signal ICs.

Silicon measurements show an excellent correlation with PN Aware results also with passive and active shielding layout strategies including floating and biased wells.

PN Aware v1 is available in the following technologies: XFAB XH018

Substrate model

The proprietary substrate model developed in more than 10 years of research at the Swiss Federal Institute of Technology of Lausanne (EPFL) includes transport of both majority and minority carriers allowing the simulation of parasitic bipolar transistors (BJT).

Model cards

The model is provided in verilog-A format and uses specific process parameters for a given technological process. PN Solutions offers also parameter calibration services for new technology nodes since it is fully compliant with all HV CMOS and BCD processes.

No-extra tools

PN Aware netlist is compatible with all spice-like circuit simulators. From the layout extraction, you can simulate your original schematic will the substrate parasitic components and visualize areas of current crowding and voltage shifts. Check the floorplan and the shielding strategies in easy way!

Layout extraction

The advanced extraction algorithms allow to extract from the IC layout the substrate netlist including lateral NPN BJTs and vertical PNP BJTs. Several options are available to set the accuracy and the simulation speed for small and large circuits.

Optimize your area

Layout distances between different wells are a key feature to reduce latch-up risk in your IC. PN Aware tracks all the distance effects in the floorplan allowing to optimize the area in the more efficient way against substrate couplings.

Fast and reliable

Among the other key benefits, designers can explore the substrate couplings between different power domains. Industrial chip measurements show a good correlation with simulated results from low to high current regimes.